1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of forming self-aligned low resistance contact layers on a semiconductor device.
2. Discussion of Related Art
Low resistance contact layers, such as salicides, are commonly used to improve the performance of semiconductor devices, for example the transistor. Typically, the fabrication of salicides on a transistor involves the formation of self-aligned silicide layers on the source and drain regions. One of the advantages of using salicides is to improve the parasitic resistance in the source and drain diffusion regions that often results from the downscaling of source and drain dimensions.
FIGS. 1A-1D illustrate a conventional method of forming salicides on a typical transistor. Referring to FIG. 1A, the transistor comprises a substrate 100 having a gate dielectric layer 140 formed thereon. A poly-silicon gate 150 is formed on the gate dielectric layer 140. A cap layer 162 is formed on the top of the poly-silicon gate 150. Spacers 164, 166 are formed on the sidewalls of the poly-silicon gate 150. The substrate 100 comprises source and drain regions 110, 120 that are formed at opposite sides of the poly-silicon gate 150.
Next, an implant-based pre-amorphization step is performed on the substrate 100. The implant-based pre-amorphization step utilizes neutral species implants 200, such as germanium (Ge), to convert the monocrystalline source and drain regions 110, 120 into amorphous silicon regions 111, 121, as shown in FIG. 1B. Subsequently, in FIG. 1C, a metal layer 180 is blanket deposited on the substrate 100. Then, an annealing process is performed on the substrate 100, which causes the amorphous silicon regions 111, 121 to react with the portions of the metal layer 180 deposited thereon and form salicide regions 181, 182 in the substrate 100, as shown in FIG. 1D.
The method illustrated in FIGS. 1A-1D utilizes an implant-based pre-amorphization step to create amorphous silicon regions 111, 121 in the source, drain regions 110, 120. As a result, the thickness and profile of the salicide regions 181, 182 are dependent on the implant profile of the amorphous silicon regions 111, 121 formed during the implant-based pre-amorphization step. Thus, a non-uniform implant profile in the amorphous silicon regions 111, 121 can cause non-uniform formation of the salicide regions 181, 182 which affects the resistivity of the salicide regions 181, 182. Furthermore, possible recessing of the substrate 100 due to excessive consumption by the metal layer 180 causes high junction leakage. A two step annealing process can be used to rectify these problems but it increases the number of thermal cycle which causes dopant deactivation, dopant diffusion as well as junction leakage.